This invention generally relates to a method and an apparatus for providing a phase locked loop circuit and in particular to providing a phase locked loop having a free-running mode.
Phase locked loop circuits are widely used in many different applications, such as in communication and networking systems. For example, microprocessor chips require on-chip clock generation. A phase locked loop enables a precise tracking and phase locking of a synthesized clock signal to a reference clock signal.
Some prior art phase locked loops operate based on analog algorithms. Such systems are subject to very large phase errors and are heavily influenced by random noise. Because of the analog nature of such systems they are difficult to highly integrate. Also, functions such as a divide by N or edge registration are difficult to implement in an integrated device. Analog systems are also relatively susceptible to loss of phase lock or incapability of obtaining phase lock because of random variations in the system.
Other prior art phase locked loops operate based on digital algorithms. One such phase locked loop (PLL) is identified as MT9042B available from Mitel Corporation and is described in detail in Issue 11 of their publication xe2x80x9cDigital Switching and Networking Componentsxe2x80x9d. If network synchronization is temporarily disrupted, the MT 9042B provides timing and synchronization signals based on storage techniques. The stored values are determined during synchronized mode when an external reference signal is available and the clock is locked to the external reference signal. When the external reference signal is lost, the stored values are used to attempt to maintain the output clock signal.
Further, U.S. Pat. No. 5,883,533 in the name of Matsuda and Nogami discloses a clock signal-generating device having an active and a spare clock selecting circuit connected to a PLL circuit. This PLL circuit operates similarly as the MT9042B in that it is based on storage techniques. The PLL circuit includes a holdover circuit for temporarily holding a signal output from the selecting circuit for a preselected period of time.
Similarly, U.S. Pat. No. 5,910,740 by Underwood discloses a phase locked loop having memory. This PLL also has a memory that enables highly precise tracking and phase locking of a synthesized clock signal to its reference clock signal.
It is an object of the present invention to provide a PLL having a slower frequency shift process at the PLL output in comparison to prior art PLLs.
Advantageously, the PLL in accordance with the invention allows the system clock to run long enough and stable enough for the PLL system to issue a fault report through another logic and memory device when the reference clock signal is lost.
In accordance with the invention there is provided a charge pump phase locked loop circuit for providing an output clock signal comprising: an input port for receiving a reference clock signal; a detector for receiving the reference clock signal and for detecting oscillations of the reference clock signal, the detector for comparing the output clock signal and the reference clock signal and determining an acceptability of the reference clock signal, for providing a first signal indicative of one of the reference clock signal being accepted as a reference clock and the reference clock signal being accepted as other than a reference clock; a charge pump circuit having output port, the charge pump circuit for providing a drive signal for varying a phase of the output clock signal and for receiving the first signal, the charge pump circuit for providing high impedance at the output port when the first signal indicates that the reference clock signal is accepted as other than a reference clock at the input port.
In accordance with another aspect of the invention there is further provided a method of providing a free-running mode for a phase locked loop including a charge pump circuit having an output port comprising the steps of: receiving a reference clock signal at an input port; determining oscillations of the received reference clock signal; determining an acceptability of the reference clock signal; providing a first signal to the charge pump circuit when the reference clock signal has a quality below a predetermined level; and providing high impedance at the output port of the charge pump circuit upon receipt of the first signal.